Test circuitry is often included within a semiconductor device die so that self test procedures can be utilized after manufacture of the semiconductor device die. Having self test circuitry built into the semiconductor device die often improves test cycle time; however, this self test circuitry consumes a portion of the die area thereby increasing the size for the resulting semiconductor package for the die. Further, this self test circuit can also require externally accessible test connection pads that are electrically active, and these test pads can lead to misuse by customers. For example, a semiconductor die can include one or more pins on a package that are only used during test procedures. These test-only pins can lead to incorrect use or treatment by end customers that lead to device failures. Further, even when properly grounded by the end customer, such test-only pins still must meet full ESD (electro-static discharge) and latch-up requirements for external pins in order to achieve customer qualification. Thus, while it is efficient for test purposes to include test circuitry within the semiconductor die, this on-chip test circuitry can require increased die and package sizes and lead to problems from customer misuse.
FIG. 1 (Prior Art) is a top view diagram of an embodiment 100 for a plurality of semiconductor device dice formed on a semiconductor substrate. As represented with respect to die 110, each of the dice include test circuitry (T) 114 and a sealring 112. The sealring 112 provides a protective metal barrier for the internal device circuitry within the die 110, such as test circuitry 114. The sealring 112 is formed using metal layers and metal vias through dielectric layers that lie between the metal layers. The structures for the sealring 112 are formed during semiconductor processing steps used to form the device circuitry for the semiconductor device dice. Scribe lanes 102, 104, and 106 are also shown for embodiment 100. The scribe lanes 102/104/106 represent relative locations where one or more cuts will be made to singulate the semiconductor device dice once the semiconductor processing steps for the semiconductor substrate are completed. It is noted that while only a few dice are shown in embodiment 100, additional semiconductor dice and related scribe lanes would be provided across the entire semiconductor substrate, such as a semiconductor wafer, being used to manufacture the semiconductor device dice. Once singulated, these semiconductor dice are packaged in various ways to form packaged integrated circuits.
FIG. 2 (Prior Art) is a cross-section view of an embodiment 200 for sealring structures 209/219 positioned on either side of a scribe lane 104. For the embodiment 200 shown, a first die (DIE1) 110A is located to the left of scribe lane 104, and a second die (DIE2) 110B is located to the right of scribe lane 104. The first die 110A includes device circuitry 204 formed within a semiconductor substrate using one or more processing steps, and first die 110A includes device metal interconnect layers 202 that are formed above the semiconductor substrate using one or more processing steps. The first die 110A also includes a guard region 208 within the semiconductor substrate, and a sealring region 206 above the guard ring region 208. The sealring region 206 includes the sealring structure 209 that is formed using a plurality of metal layers and metal vias between the metal layers. Similarly, the second die 110B includes device circuitry 214 formed within a semiconductor substrate using one or more processing steps, and second die 110B includes device interconnect layers 212 that are formed above the semiconductor substrate using one or more processing steps. The second die 110B also includes a guard region 218 within the semiconductor substrate, and a sealring region 216 above the guard region 218. The sealring region 216 includes the sealring structure 219 that is formed using a plurality of metal layers and metal vias between the metal layers. For embodiment 200, the sealring structures 209 and 219 have been formed using six metal layers (L1, L2, L3, L4, L5, L6) and metal vias through non-conductive layers that lie between these metal layers. When one or more cuts are made within the scribe lane 104 to singulate the semiconductor dice 110A/110B, the sealring structures 209/219 will be left at the edge of the dice 110A/110B to form a protective metal barrier that extends from the surface of the die to the substrate. It is also noted that the sealring structures 209/219 can be implemented with different and/or more complicated structures, including multiple ring stacks and/or other desired structures or combinations of structures. It is again noted that sealring structures are typically used for protective purposes, such as to reduce edge cracks, to reduce ionic contamination, and/or to serve other protective purposes.